1. Field of the Invention
The present invention generally relates to a method of fabrication of Mask ROM, and more precisely to a method of fabrication of new type of Trench Mask ROM.
2. Background of the Related Art
As the complexity and performance of ICs increase, more processing steps are needed to fabricate them. Four or five mask levels were quite adequate for primitive ICs in the 1970s, whereas 16-Mb (ultra large-scale integration or ULSI) memory chips require more than twenty mask levels. For bit densities of up to one megabit, planartype storage capacitors are used.
Read Only Memory is so named because its cells can read data only from the memory cells. The ROM can be distinguished as Mask ROM, PROM (Programmable ROM), EPROM (Erasable Programmable ROM) and EEPROM (Electrically Erasable Programmable ROM) depending on the particular method a ROM uses to store data. The Mask ROM is most fundamental ROM.
The fabrication of a typical planar type of Mask ROM is described as follows. The description of the process sequence for forming a planar type of Mask ROM is as shown in FIG. 1a to FIG. 1e. Referring first to FIG. 1a, a portion of the substrate 100 lightly with p-type dopant is shown. Furthermore, there are field-oxide areas 106 on both sides of the top portion of the substrate 100. A photo resist 104 is formed on the outer surface of the substrate 100 to define plural doped regions 102. The plural doped regions 102 are formed using an ion-implanting technique, wherein the plural doped regions 102 are implanted with n.sup.+ -type ion, such as As or P. The photo resist 104 is removed and the photo resist 104 is used to define the doped regions 102. Referring to FIG. 1b, after removing the photo resists 104 boron ions are implanted into the substrate to form cell isolation region 108. The cell isolation region 24 is used for suppressing the leakage. Referring to FIG. 1c, a gate oxide layer 110 is formed on the substrate 100 and the doped regions 102. And, a polysilicon layer 112 is formed sequentially on the gate oxide layer 110.
Referring to FIG. 1d, a photo mask 114 is used during a boron ion-implanting step, wherein the photo mask 114 is used to define a coding cell for forming a Mask ROM. Then, a Mask ROM is formed with some high-logic-level regions. As shown in FIG. 1e, there is a fixed threshold voltage between two adjacent doped regions 102. According to the doped regions 102 doped with n.sup.+ -type dopant and the doped regions 116 doped with boron ions will increase the threshold voltage. Namely, a higher threshold voltage relates to a high-logic-level. Conversely, a low-logic-level is one pair of two the adjacent doped regions 102 which contains an undoped region 118 between the two adjacent doped regions 102.
However, as component density has increased, the amount of charge need for a sufficient noise margin remains fixed. And, a device is composed of huge number of components. Further, a chip contains a lot of devices. As described above, the typical planar type of Mask ROM cannot satisfy the reduction of the device scale. Hence, it is difficult to compose a huge number of devices on a small chip. Furthermore, as the size of device is reduced the distance between two adjacent components is so close so as to cause the current leakage on the surface of the device. Hence, the current leakage and small-scale integration lead the fabrication of the mask ROM to be restricted. Therefore, in order to reduce leakage and cell size and to form large-scale integration, a new type of Trench Mask ROM cell is needed.